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FEATURES Complete, Low Cost Stereo DAC System in a Single Die Package Variable Rate Oversampling Interpolation Filter Multibit Modulator with Triangular PDF Dither Discrete and Continuous Time Analog Reconstruction Filters Extremely Low Out-of-Band Energy 64 Step (1 dB/Step) Analog Attenuator with Mute Buffered Outputs with 2 k Output Load Drive Rejects Sample Clock Jitter 94 dB Dynamic Range, -88 dB THD+N Performance Option for Analog De-emphasis Processing with External Passive Components 0.1 Maximum Phase Linearity Deviation Continuously Variable Sample Rate Support Digital Phase Locked Loop Based Asynchronous Master Clock On-Chip Master Clock Oscillator, Only External Crystal Is Required Power-Down Mode Flexible Serial Data Port (I2S-Justified, Left-Justified, Right-Justified and DSP Serial Port Modes) SPI* Compatible Serial Control Port Single +5 V Supply 28-Pin SOIC and SSOP Packages APPLICATIONS Digital Cable TV and Direct Broadcast Satellite Set-Top Decoder Boxes Digital Video Disc, Video CD and CD-I Players High Definition Televisions, Digital Audio Broadcast Receivers CD, CD-R, DAT, DCC, ATAPI CD-ROM and MD Players Digital Audio Workstations, Computer Multimedia Products
Stereo, Single-Supply 18-Bit Integrated DAC AD1859
PRODUCT OVERVIEW
The AD1859 is a complete 16-/18-bit single-chip stereo digital audio playback subsystem. It comprises a variable rate digital interpolation filter, a revolutionary multibit sigma-delta () modulator with dither, a jitter-tolerant DAC, switched capacitor and continuous time analog filters, and analog output drive circuitry. Other features include an on-chip stereo attenuator and mute, programmed through an SPI-compatible serial control port. The key differentiating feature of the AD1859 is its asynchronous master clock capability. Previous audio DACs required a high frequency master clock at 256 or 384 times the intended audio sample rate. The generation and management of this high frequency synchronous clock is burdensome to the board level designer. The analog performance of conventional single bit DACs is also dependent on the spectral purity of the sample and master clocks. The AD1859 has a digital Phase Locked Loop (PLL) which allows the master clock to be asynchronous, and which also strongly rejects jitter on the sample clock (left/right clock). The digital PLL allows the AD1859 to be clocked with a single frequency (27 MHz for example) while the sample frequency (as determined from the left/right clock) can vary over a wide range. The digital PLL will lock to the new sample rate in approximately 100 ms. Jitter components 15 Hz above and below the sample frequency are rejected by 6 dB per octave. This level of jitter rejection is unprecedented in audio DACs. The AD1859 supports continuously variable sample rates with essentially linear phase response, and with an option for external analog de-emphasis processing. The clock circuit includes an on-chip oscillator, so that the user need only provide an external crystal. The oscillator may be overdriven, if desired, with an external clock source. (continued on page 7)
FUNCTIONAL BLOCK DIAGRAM
DIGITAL SUPPLY 2 CONTROL DATA INPUT 3 SERIAL CONTROL INTERFACE MULTIBIT MODULATOR MULTIBIT MODULATOR REFERENCE FILTER AND GROUND 2 DPLL/CLOCK MANAGER DE-EMPHASIS SWITCH LEFT COMMON MODE ASYNCHRONOUS CLOCK/CRYSTAL
AD1859
VARIABLE RATE INTERPOLATION VARIABLE RATE INTERPOLATION
VOLTAGE REFERENCE ANALOG FILTER ANALOG FILTER
16- OR 18-BIT 6 DIGITAL DATA INPUT
SERIAL DATA INTERFACE
DAC DAC
ATTEN/ MUTE ATTEN/ MUTE
OUTPUT BUFFER OUTPUT BUFFER 2
ANALOG OUTPUTS DE-EMPHASIS SWITCH RIGHT
POWER DOWN/RESET
MUTE
DE-EMPHASIS
ANALOG SUPPLY
*SPI is a registered trademark of Motorola, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD1859-SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD) Ambient Temperature Input Clock (FMCLK) Input Signal Input Sample Rate Measurement Bandwidth Input Data Word Width Load Capacitance Input Voltage HI (VIH) Input Voltage LO (VIL)
+5.0 V 25 C 27.1656 MHz 1001.2938 Hz -0.5 dB Full Scale 44.1 kHz 10 Hz to 20 kHz 18 Bits 100 pF 2.4 V 0.8 V
NOTES I2S-Justified Mode (Ref. Figure 3). Device Under Test (DUT) is bypassed, decoupled and dc-coupled as shown in Figure 17 (no de-emphasis circuit). Performance of the right and left channels are identical (exclusive of "Interchannel Gain Mismatch" and "Interchannel Phase Deviation" specifications). Attenuation setting is 0 dB. Values in bold typeface are tested; all others are guaranteed, not tested.
ANALOG PERFORMANCE
Min Resolution Dynamic Range (20 to 20 kHz, -60 dB Input) (No A-Weight Filter) (With A-Weight Filter) Total Harmonic Distortion + Noise Analog Outputs Single-Ended Output Range ( Full Scale) Output Impedance at Each Output Pin Output Capacitance at Each Output Pin External Load Impedance (THD +N -84 dB) Out-of-Band Energy (0.5 x FS to 100 kHz) CMOUT DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation Attenuator Step Size Attenuator Range Span Mute Attenuation De-Emphasis Switch (EMPL, EMPR) DC Resistance
DIGITAL INPUTS
Typ 18
Max
Units Bits dB dB dB % V p-p pF dB V % dB ppm/C dB Degrees dB dB dB
85.7 88
91 94 -88 0.004 3.0 17 2K 2.25 1 0.01 140
-84 0.0063 3.2 24 20 -72.5 2.45 5 0.225 270
2.8
750 2.05
101 0.6 -61.5 -70 3
0.1 1.0 -62.5 -74.2 10
1.4 -63.5 50
Min Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 2.4 V) Input Leakage (IIL @ VIL = 0.8 V) Input Capacitance 2.4
Typ
Max 0.8 6 6 20
Units V V A A pF
1 1
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AD1859
DIGITAL TIMING (Guaranteed over -40C to +105C, AVDD = DVDD = +5.0 V 10%) Min tDBH tDBL tDBP tDLS tDLH tDDS tDDH tCCH tCCL tCCP tCSU tCHD tCLD tCLL tCLH tPDRP tMCP FMC tMCH tMCL POWER Min Supplies Voltage, Analog and Digital Analog Current Analog Current--Power Down Digital Current Digital Current--Power Down Dissipation Operation--Both Supplies Operation--Analog Supply Operation--Digital Supply Power Down--Both Supplies Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins TEMPERATURE RANGE Min Specifications Guaranteed Functionality Guaranteed Storage PACKAGE CHARACTERISTICS Typ SOIC JA (Thermal Resistance [Junction-to-Ambient]) SOIC JC (Thermal Resistance [Junction-to-Case]) SSOP JA (Thermal Resistance [Junction-to-Ambient]) SSOP JC (Thermal Resistance [Junction-to-Case]) 120.67 13.29 190.87 15.52 Units C/W C/W C/W C/W -40 -55 Typ 25 +105 +125 Max Units C C C 4.5 29.5 23.5 Typ 5 36 0.5 30 6 265 147.5 117.5 30 55 52 Max 5.5 mA 15 mA 9.5 330 180 150 48 Units V A mA mW mW mW mW dB dB BCLK HI Pulse Width BCLK LO Pulse Width BCLK Period LRCLK Setup LRCLK Hold (DSP Serial Port Style Mode Only) SDATA Setup SDATA Hold CCLK HI Pulse Width CCLK LO Pulse Width CCLK Period CDATA Setup CDATA Hold CLATCH Delay CLATCH LO Pulse Width CLATCH HI Pulse Width PD/RST LO Pulse Width MCLK Period MCLK Frequency (1/tMCP) MCLK HI Pulse Width MCLK LO Pulse Width Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 25 50 5 0 0 5 15 15 30 0 5 15 5 10 4 MCLK Periods (150 ns @ 27 MHz) 30 37 17 27 15 15
60 33
ns MHz ns ns
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ABSOLUTE MAXIMUM RATINGS* DVDD to DGND AVDD to AGND Digital Inputs Analog Inputs AGND to DGND Reference Voltage Soldering Min Typ Max -0.3 6 -0.3 6 DGND - 0.3 DVDD + 0.3 AGND - 0.3 AVDD + 0.3 -0.3 0.3 Indefinite Short Circuit to Ground +300 10 Units V V V V V C sec
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DIGITAL FILTER CHARACTERISTICS Min Passband Ripple Stopband1 Attenuation 48 kHz FS Passband Stopband 44.1 kHz FS Passband Stopband 32 kHz FS Passband Stopband Other FS Passband Stopband Group Delay Group Delay Variation ANALOG FILTER CHARACTERISTICS Min Passband Ripple Stopband Attenuation (at 64 x FS) 58 Typ Max -0.075 Units dB dB 62 0 26.688 0 24.520 0 17.792 0 0.556 21.312 6117 19.580 5620 14.208 4078 0.444 127.444 40/FS 0 Typ Max 0.045 Units dB dB kHz kHz kHz kHz kHz kHz FS FS sec s
NOTE 1 Stopband nominally repeats itself at multiples of 128 x FS, where FS is the input word rate. Thus the digital filter will attenuate to 62 dB across the frequency spectrum except for a range 0.55 x FS wide at multiples of 128 x FS.
PIN CONNECTIONS ORDERING GUIDE
CMOUT DEEMP EMPL 1 2 3 4 5 6 7 8 9 28 FILT 27 FGND 26 EMPR 25 OUTR 24 NC
Model AD1859JR AD1859JRS
Temperature Range -40C to +105C -40C to +105C
Package Description 28-Lead SOIC 28-Lead SSOP
Package Option R-28 RS-28
OUTL NC AGND MUTE 18/16 IDPM0
AD1859
TOP VIEW (Not to Scale)
23 AVDD 22 NC 21 CLATCH 20 CDATA 19 CCLK 18 DGND 17 DVDD 16 XTALI/MCLK 15 XTALO
IDPM1 10 PD/RST 11 SDATA 12 LRCLK 13 BCLK 14
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1859 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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DEFINITIONS Dynamic Range Gain Error
The ratio of a full-scale output signal to the integrated output noise in the passband (0 to 20 kHz), expressed in decibels (dB). Dynamic range is measured with a -60 dB input signal and is equal to (S/[THD+N]) + 60 dB. Note that spurious harmonics are below the noise with a -60 dB input, so the noise level establishes the dynamic range. This measurement technique is consistent with the recommendations of the Audio Engineering Society (AES17-1991) and the Electronics Industries Association of Japan (EIAJ CP-307).
Total Harmonic Distortion + Noise (THD+N)
With a near full-scale input, the ratio of actual output to expected output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per C.
Crosstalk (EIAJ method)
The ratio of the root-mean-square (rms) value of a full-scale fundamental input signal to the rms sum of all other spectral components in the passband, expressed in decibels (dB) and percentage.
Passband
Ratio of response on one channel with a zero input to a full-scale 1 kHz sine-wave input on the other channel, expressed in decibels.
Interchannel Phase Deviation
Difference in output sampling times between stereo channels, expressed as a phase difference in degrees between 1 kHz inputs.
Power Supply Rejection
The region of the frequency spectrum unaffected by the attenuation of the digital interpolation filter.
Passband Ripple
With zero input, signal present at the output when a 300 mV p-p signal is applied to power supply pins, expressed in decibels of full scale.
Group Delay
The peak-to-peak variation in amplitude response from equalamplitude input signal frequencies within the passband, expressed in decibels.
Stopband
The region of the frequency spectrum attenuated by the digital interpolation filter to the degree specified by "stopband attenuation."
Intuitively, the time interval required for an input pulse to appear at the converter's output, expressed in seconds (s). More precisely, the derivative of radian phase with respect to radian frequency at a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies. Specified as the difference between the largest and the smallest group delays in the passband, expressed in microseconds (s).
PIN DESCRIPTIONS Digital Audio Serial Input Interface
Serial Control Port Interface Pin Name Number CDATA 20 I/O I Description Serial control input, MSB first, containing 8 bits of unsigned data per channel. Used for specifying channel specific attenuation and mute. Control clock input for control data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. Latch input for control data. This input is rising edge sensitive.
Pin Name Number SDATA 12
I/O I
Description Serial input, MSB first, containing two channels of 16 or 18 bits of twos complement data per channel. Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion. Left/right clock input for input data. Must run continuously. Input serial data port mode control zero. With IDPM1, defines one of four serial input modes. Input serial data port mode control one. With IDPM0, defines one of four serial input modes. 18-bit or 16-bit input data mode control. Connect this signal HI for 18-bit input mode, LO for 16-bit input mode.
BCLK
14
I
CCLK
19
I
LRCLK IDPM0
13 9
I I
CLATCH
21
I
IDPM1
10
I
18/16
8
I
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AD1859
PIN DESCRIPTIONS
Analog Signals
Pin Name FILT Number 28 I/O Description O Voltage reference filter capacitor connection. Bypass and decouple the voltage reference with parallel 10 F and 0.1 F capacitors to the FGND pin. Voltage reference filter ground. Use exclusively for bypassing and decoupling of the FILT pin (voltage reference). Voltage reference common-mode output. Should be decoupled with 10 F capacitor to the AGND pin or plane. This output is available externally for dc-coupling and levelshifting. CMOUT should not have any signal dependent load, or where it will sink or source current. Left channel line level analog output. Right channel line level analog output. De-emphasis switch connection for the left channel. Can be left unconnected if de-emphasis is not required in the target application. De-emphasis switch connection for the right channel. Can be left unconnected if de-emphasis is not required in the target application.
Control and Clock Signals
Pin Name PD/RST Number 11 I/O Description I Power down/reset. The AD1859 is placed in a low power consumption "sleep" mode when this pin is held LO. The AD1859 is reset on the rising edge of this signal. The serial control port registers are reset to their default values. Connect HI for normal operation. De-emphasis. An external analog deemphasis circuit network is enabled when this input signal is HI. This circuit is typically used to impose a 50/15 s (or perhaps the CCITT J.17) response characteristic on the output audio spectrum. Mute. Assert HI to mute both stereo analog outputs of the AD1859. Deassert LO for normal operation. Crystal input or master clock input. Connect to one side of a quartz crystal to this input, or connect to an external clock source to overdrive the on-chip oscillator. Crystal output. Connect to other side of a quartz crystal. Do not connect if using the XTALI/MCLK pin with an external clock source.
FGND
27
I
DEEMP
2
I
CMOUT
1
O
MUTE
7
I
OUTL OUTR EMPL
4 25 3
O O O
XTALI/ MCLK
16
I
EMPR
26
O
XTALO
15
O
Power Supply Connections and Miscellaneous
Pin Name AVDD AGND DVDD DGND NC Number 23 6 17 18 5, 22, 24 I/O Description I I I I Analog Power Supply. Connect to analog +5 V supply. Analog Ground. Digital Power Supply. Connect to digital +5 V supply. Digital Ground. No Connect. Reserved. Do not connect.
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(continued from page 1) The AD1859 has a simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The serial data input port can be configured in left-justified, I2S-justified, right-justified and DSP serial port compatible modes. The AD1859 accepts 16- or 18-bit serial audio data in MSB-first, twos-complement format. A power-down mode is offered to minimize power consumption when the device is inactive. The AD1859 operates from a single +5 V power supply. It is fabricated on a single monolithic integrated circuit using a 0.6 M CMOS double polysilicon, double metal process, and is housed in 28-pin SOIC and SSOP packages for operation over the temperature range -40C to +105C.
THEORY OF OPERATION
the fourth stage is a second-order comb filter. The FIR filter implementation is multiplier-free, i.e., the multiplies are performed using shift-and-add operations.
Multibit Sigma-Delta Modulator
The AD1859 offers the advantages of sigma-delta conversion architectures (no component trims, low cost CMOS process technology, superb low level linearity performance) with the advantages of conventional multibit R-2R resistive ladder audio DACs (no requirement for any high frequency synchronous master clocks [e.g., 256 or 384 x FS] continuously variable sample rate support, jitter tolerance, low output noise, etc.). The use of a multibit sigma-delta modulator means that the AD1859 generates dramatically lower amounts of out-of-band noise energy, which greatly reduces the requirement on post DAC filtering. The required post-filtering is integrated on the AD1859. The AD1859's multibit sigma-delta modulator is also highly immune to digital substrate noise. The digital phase locked loop feature gives the AD1859 an unprecedented jitter rejection feature. The bandwidth of the first order loop filter is 15 Hz; jitter components on the input left/right clock are attenuated by 6 dB per octave above and below 15 Hz. Jitter on the crystal time base or MCLK input is rejected as well (by virtue of the on-chip switched capacitor filter), but this clock should be low jitter because it is used by the DAC to convert the audio from the discrete time (sampled) domain to the continuous time (analog) domain. The AD1859 includes an on-chip oscillator, so that the user need only provide an inexpensive quartz crystal or ceramic resonator as an external time base.
Serial Audio Data Interface
The AD1859 employs a four-bit sigma-delta modulator. Whereas a traditional single bit sigma-delta modulator has two levels of quantization, the AD1859's has 17 levels of quantization. Traditional single bit sigma-delta modulators sample the input signal at 64 times the input sample rate; the AD1859 samples the input signal at nominally 128 times the input sample rate. The additional quantization levels combined with the higher oversampling ratio means that the AD1859 DAC output spectrum contains dramatically lower levels of out-of-band noise energy, which is a major stumbling block with more traditional single bit sigmadelta architectures. This means that the post-DAC analog reconstruction filter has reduced transition band steepness and attenuation requirements, which equates directly to lower phase distortion. Since the analog filtering generally establishes the noise and distortion characteristic of the DAC, the reduced requirements translate into better audio performance. Multibit sigma-delta modulators bring an additional benefit: they are essentially free of stability (and therefore potential loop oscillation) problems. They are able to use a wider range of the voltage reference, which can increase the overall dynamic range of the converter. The conventional problem which limits the performance of multibit sigma delta converters is the nonlinearity of the passive circuit elements used to sum the quantization levels. Analog Devices has developed (and been granted patents on) a revolutionary architecture which overcomes the component linearity problem that otherwise limits the performance of multibit sigma delta audio converters. This new architecture provides the AD1859 with the same excellent differential nonlinearity and linearity drift (over temperature and time) specifications as single bit sigma-delta DACs. The AD1859's multibit modulator has another important advantage; it has a high immunity to substrate digital noise. Substrate noise can be a significant problem in mixed-signal designs, where it can produce intermodulation products that fold down into the audio band. The AD1859 is approximately eight times less sensitive to digital substrate noise (voltage reference noise injection) than equivalent single bit sigma-delta modulator based DACs.
Dither Generator
The serial audio data interface uses the bit clock (BCLK) simply to clock the data into the AD1859. The bit clock may, therefore, be asynchronous to the L/R clock. The left/right clock (LRCLK) is both a framing signal, and the sample frequency input to the digital phase locked loop. The left/right clock (LRCLK) is the signal that the AD1859 actually uses to determine the input sample rate, and it is the jitter on LRCLK that is rejected by the digital phase locked loop. The SDATA input carries the serial stereo digital audio in MSB first, twos-complement format.
Digital Interpolation Filter
The AD1859 includes an on-chip dither generator, which is intended to further reduce the quantization noise introduced by the multibit DAC. The dither has a triangular Probability Distribution Function (PDF) characteristic, which is generally considered to create the most favorable noise shaping of the residual quantization noise. The AD1859 is among the first low cost, IC audio DACs to include dithering.
Analog Filtering
The purpose of the interpolator is to "oversample" the input data, i.e., to increase the sample rate so that the attenuation requirements on the analog reconstruction filter are relaxed. The AD1859 interpolator increases the input data sample rate by a variable factor depending on the sample frequency of the incoming digital audio. The interpolation is performed using a multistage FIR digital filter structure. The first stage is a droop equalizer; the second and third stages are half-band filters; and
The AD1859 includes a second-order switched capacitor discrete time low-pass filter followed by a first-order analog continuous time low-pass filter. These filters eliminate the need for any additional off-chip external reconstruction filtering. This on-chip switched capacitor analog filtering is essential to reduce the deleterious effects of any remaining master clock jitter.
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AD1859
Option for Analog De-emphasis Processing
The AD1859 includes three pins for implementing an external analog 50/15 s (or possibly the CCITT J. 17) de-emphasis frequency response characteristic. A control pin DEEMP (Pin 2) enables de-emphasis when it is asserted HI. Two analog outputs, EMPL (Pin 3) and EMPR (Pin 26) are used to switch the required analog components into the output stage of the AD1859. An analog implementation of de-emphasis is superior to a digital implementation in several ways. It is generally lower noise, since digital de-emphasis is usually created using recursive IIR filters, which inject limit cycle noise. Also the digital de-emphasis is being applied in front of the primary analog noise generation source, the DAC modulator, and its high frequency noise contributions are not attenuated. An analog de-emphasis circuit is downstream from the relatively "noisy" DAC modulator and thus provides a more effective noise reduction role (which was the original intent of the emphasis/de-emphasis scheme). A final key advantage of analog de-emphasis is that it is sample rate invariant, so that users can fully exploit the sample rate range of the AD1859 and simultaneously use de-emphasis. Digital implementations generally only support fixed, standard sample rates.
Digital Phase Locked Loop
The phase detector automatically switches the loop filter into "slow" mode as phase lock is gradually obtained. The loop bandwidth is 15 Hz in slow mode. Since the loop filter is first order, the digital PLL will reject jitter on the left/right clock above 15 Hz, with an attenuation of 6 dB per octave. The jitter rejection frequency response is shown in Figure 1.
0 -6
JITTER ATTENUATION - dB
-12 -18 -24 -30 -36 -42 -48 -54 -60 0 15 30 60 120 240 480 960 1920 3840 7680 15360 Hz ABOVE OR BELOW THE SAMPLE FREQUENCY
The digital PLL is adaptive, and locks to the applied sample rate (on the LRCLK Pin 13) in 100 ms to 200 ms. The digital PLL is initially in "fast" mode, with a wide lock capture bandwidth.
Figure 1. Digital PLL Jitter Rejection
OPERATING FEATURES Serial Data Input Port
Serial Input Port Modes
The AD1859 uses the frequency of the left/right input clock to determine the input sample rate. LRCLK must run continuously and transition twice per stereo sample period (except in the left-justified DSP serial port style mode, when it transitions four times per stereo sample period). The bit clock (BCLK) is edge sensitive and may be used in a gated or burst mode (i.e., a stream of pulses during data transmission followed by periods of inactivity). The bit clock is only used to write the audio data into the serial input port. It is important that the left/right clock is "clean" with monotonic rising and falling edge transitions and no excessive overshoot or undershoot which could cause false clock triggering of the AD1859. The AD1859's flexible serial data input port accepts data in twos-complement, MSB-first format. The left channel data field always precedes the right channel data field. The input data consists of either 16 or 18 bits, as established by the 18/16 input control (Pin 8). All digital inputs are specified to TTL logic levels. The input data port is configured by control pins.
The AD1859 uses two multiplexed input pins to control the mode configuration of the input data port. IDPM0 and IDPM1 program the input data port mode as follows: IDPM1 LO LO HI HI IDPM0 LO HI LO HI Serial Input Port Mode Right-Justified (See Figure 2) I2S-Justified (See Figure 3) Left-Justified (See Figure 4) Left-Justified DSP Serial Port Style (See Figure 5)
Figure 2 shows the right-justified mode. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is delayed 14-bit clock periods (in 18-bit input mode) or 16-bit clock periods (in 16-bit input mode) from an LRCLK transition, so that when there are 64 BCLK periods per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition.
LRCLK INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK INPUT SDATA INPUT
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
Figure 2. Right-Justified Mode
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Figure 3 shows the I2S-justified mode. LRCLK is LO for the left channel, and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition but with a single BCLK period delay. The I2S-justified mode can be used in either the 16-bit or the 18-bit input mode. Figure 4 shows the left-justified mode. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay. The left-justified mode can be used in either the 16-bit or the 18-bit input mode. Figure 5 shows the left-justified DSP serial port style mode. LRCLK must pulse HI for at least one bit clock period before the MSB of the left channel is valid, and LRCLK must pulse HI again for at least one bit clock period before the MSB of the right channel is valid. Data is valid on the falling edge of BCLK. The left-justified DSP serial port style mode can be used in either the 16-bit or the 18-bit input mode. Note that in this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse, and that the right data is transmitted with the second LRCLK pulse, and that synchronism is maintained from that point forward. Note that in 16-bit input mode, the AD1859 is capable of a 32 x FS BCLK frequency "packed mode" where the MSB is leftjustified to an LRCLK transition, and the LSB is right-justified to an LRCLK transition. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. Packed mode can be used when the AD1859 is programmed in either right-justified or left-justified mode. Packed mode is shown in Figure 6.
Serial Control Port
The AD1859 serial control port is SPI compatible. SPI (Serial Peripheral Interface) is a serial port protocol popularized by Motorola's family of microcomputer and microcontroller products. The write-only serial control port gives the user access to channel specific mute and attenuation. The AD1859 serial control port consists of three signals, control clock CCLK (Pin 19), control data CDATA (Pin 20), and control latch CLATCH (Pin 21). The control data input (CDATA) must be valid on the control clock (CCLK) rising edge, and the control clock (CCLK) must only make a LO to HI transition when there is valid data. The control latch (CLATCH) must make a LO to HI transition after the LSB has been clocked into the AD1859, while the control clock (CCLK) is inactive. The timing relation between these signals is shown in Figure 7.
LRCLK INPUT BCLK INPUT SDATA INPUT
MSB MSB-1 MSB-2
LEFT CHANNEL
RIGHT CHANNEL
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
Figure 3. I2S-Justified Mode
LRCLK INPUT BCLK INPUT SDATA INPUT
MSB MSB-1 MSB-2
LEFT CHANNEL
RIGHT CHANNEL
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
Figure 4. Left-Justified Mode
LRCLK INPUT BCLK INPUT SDATA INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB-1
LSB+2
LSB+1
LSB
MSB
MSB-1
LSB+2
LSB+1
LSB
MSB
MSB-1
Figure 5. Left-Justified DSP Serial Port Style Mode
LRCLK INPUT BCLK INPUT SDATA INPUT
LSB MSB
LEFT CHANNEL
RIGHT CHANNEL
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
Figure 6. 32 x FS Packed Mode
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CCLK CDATA D7 MSB CLATCH D6 D5 D4 D3 D2 D1 D0 LSB D7 MSB D6 D5
Figure 7. Serial Control Port Timing
MSB DATA7 LEFT/RIGHT Right Channel = HI Left Channel = LO DATA6 Mute Mute = HI Normal = LO DATA5 Atten5 DATA4 Atten4 DATA3 Atten3 00 00 00 00 00 00 00 00 00 = = = = = = = = = * * * 11 1101 = 11 1110 = 11 1111 = 0000 0001 0010 0011 0100 0101 0110 0111 1000 DATA2 Atten2 0.0dB -1.0dB -2.0dB -3.0dB -4.0dB -5.0dB -6.0dB -7.0dB -8.0dB DATA1 Atten1 LSB DATA0 Atten0
-61.0dB -62.0dB -63.0dB
Figure 8. Serial Control Bit Definitions
The serial control port is byte oriented. The data is MSB first, and is unsigned. There is a control register for the left channel and a control register for the right channel, as distinguished by the MSB (DATA7). The bits are assigned as shown in Figure 8. The left channel control register and the right channel control register have identical power up and reset default settings. DATA6, the Mute control bit, reset default state is LO, which is the normal (nonmuted) setting. DATA5:0, the Atten5 through Atten0 control bits, have a reset default value of 00 0000, which is an attenuation of 0.0 dB (i.e., full scale, no attenuation). The intent with these reset defaults is to enable AD1859 applications without requiring the use of the serial control port. For those users that do not use the serial control port, it is still possible to mute the AD1859 output by using the external MUTE (Pin 7) signal. It is recommended that the output be muted for approximately 1000 input sample periods during power-up or following any radical sample rate change (>5%) to allow the digital phase locked loop to settle. Note that the serial control port timing is asynchronous to the serial data input port timing. Changes made to the attenuator level will be updated on the next edge of the LRCLK after the CLATCH write pulse. The AD1859 has been designed to resolve the potential for metastability between the LRCLK edge and the CLATCH write pulse rising edge. The attenuator setting is guaranteed to be valid even if the LRCLK edge and the CLATCH rising edge occur essentially simultaneously.
On-Chip Oscillator and Master Clock
Highest Sample Rate = Master Clock Frequency / 512 The lowest sample rate supported can be computed as follows: Lowest Sample Rate = Master Clock Frequency / 1024
AD1859
XTALI/MCLK XTALO
AD1859
XTALI/MCLK XTALO NC
20-64pF
27MHz
20-64pF
27MHz 27MHz OSCILLATOR CONNECTION
27MHz CRYSTAL CONNECTION
Figure 9. Crystal and Oscillator Connections
Figure 10 illustrates these relations. As can be seen in Figure 10, a 27 MHz MCLK or crystal frequency supports audio sample rates from approximately 28 kHz to 52 kHz.
L/R CLOCK SAMPLE FREQUENCY - kHz
76 68 60 52 44 36 28 20
18 20 22 24 26 28 30 32 XTAL/MCLK FREQUENCY - MHz 34 36 LOWEST L/R SAMPLE RATE (MCLK/1024) HIGHEST L/R SAMPLE RATE (MCLK/512)
The asynchronous master clock of the AD1859 can be supplied by either an external clock source applied to XTALI/MCLK or by connecting a crystal across the XTALI/MCLK and XTALO pins, and using the on-chip oscillator. If a crystal is used, it should be fundamental-mode and parallel-tuned. Figure 9 shows example connections. The range of audio sample rates (as determined from the LRCLK input) supported by the AD1859 is a function of the master clock rate (i.e., the crystal frequency or external clock source frequency) applied. The highest sample rate supported can be computed as follows:
Figure 10. MCLK Frequency vs. L/R Clock Frequency
Mute and Attenuation
The AD1859 offers two methods of muting the analog output. By asserting the MUTE (Pin 7) signal HI, both the left channel and the right channel are muted. As an alternative, the user can assert the mute bit in the serial control registers HI for individual mute of either the left channel or the right channel. The -10- REV. A
AD1859
AD1859 has been designed to minimize pops and clicks when muting and unmuting the device. The AD1859 includes a zero crossing detector which attempts to implement attenuation changes on waveform zero crossings only. If a zero crossing is not found within 1024 input sample periods (approximately 23 ms at 44.1 kHz), the attenuation change is made regardless.
Output Drive, Buffering and Loading APPLICATIONS ISSUES Interface to MPEG Audio Decoders
Figure 11 shows the suggested interface to the Analog Devices ADSP-21xx family of DSP chips, for which several MPEG audio decode algorithms are available. The ADSP-21xx supports 16 bits of data using a left-justified DSP serial port style format.
SCLK 14 BCLK NC 13 LRCLK 12 SDATA HI NC HI LO 9 IDPM0 10 IDPM1 8 18/16
The AD1859 analog output stage is able to drive a 2 k load. If lower impedance loads must be driven, an external buffer stage such as the Analog Devices SSM2142 should be used. The analog output is generally ac coupled with a 10 F capacitor, even if the optional de-emphasis circuit is not used, as shown in Figure 17. It is possible to dc couple the AD1859 output into an op amp stage using the CMOUT signal as a bias point.
On-Chip Voltage Reference
ADSP-21xx
RFS TFS DT DR
AD1859
The AD1859 includes an on-chip voltage reference that establishes the output voltage range. The nominal value of this reference is +2.25 V which corresponds to a line output voltage swing of 3 V p-p. The line output signal is centered around a voltage established by the CMOUT (common mode) output (Pin 1). The reference must be bypassed both on the FILT input (Pin 28) with 10 F and 0.1 F capacitors, and on the CMOUT output (Pin 1) with a 10 F and 0.1 F capacitors, as shown in Figures 17 and 18. The FILT pin must use the FGND ground, and the CMOUT pin must use the AGND ground. The on-chip voltage reference may be overdriven with an external reference source by applying this voltage to the FILT pin. CMOUT and FILT must still be bypassed as shown in Figures 17 and 18. An external reference can be useful to calibrate multiple AD1859 DACs to the same gain. Reference bypass capacitors larger than those suggested can be used to improve the signal-to-noise performance of the AD1859.
Power Down and Reset
Figure 11. Interface to ADSP-21xx
Figure 12 shows the suggested interface to the Texas Instruments TMS320AV110 MPEG audio decoder IC. The TMS320AV110 supports 18 bits of data using a right-justified output format.
TEXAS INSTRUMENTS TMS320AV110 SCLK LRCLK PCMDATA PCMCLK 48 x FS TO 1536 x FS LO LO HI 14 BCLK 13 LRCLK 12 SDATA 9 IDPM0 10 IDPM1 8 18/16
AD1859
Figure 12. Interface to TMS320AV110
Figure 13 shows the suggested interface to the LSI Logic L64111 MPEG audio decoder IC. The L64111 supports 16 bits of data using a left-justified output format.
SCLKO LSI LOGIC L64111 LRCLKO SERO SYSCLK 384 x FS OR 512 x FS LO HI LO 14 BCLK 13 LRCLK 12 SDATA 9 IDPM0 10 IDPM1 8 18/16
The PD/RST input (Pin 11) is used to control the power consumed by the AD1859. When PD/RST is held LO, the AD1859 is placed in a low dissipation power-down state. When PD/RST is brought HI, the AD1859 becomes ready for normal operation. The master clock (XTALI/MCLK, Pin 16) must be running for a successful reset or power-down operation to occur. The PD/RST signal must be LO for a minimum of four master clock periods (approximately 150 ns with a 27 MHz XTALI/MCLK frequency). When the PD/RST input (Pin 11) is asserted brought HI, the AD1859 is reset. All registers in the AD1859 digital engine (serial data port, interpolation filter and modulator) are zeroed, and the amplifiers in the analog section are shorted during the reset operation. The two registers in the serial control port are initialized to their default values. The user should wait 100 ms after bringing PD/RST HI before using the serial data input port and the serial control input port in order for the digital phase locked loop to re-acquire lock. The AD1859 has been designed to minimize pops and clicks when entering and exiting the powerdown state.
Control Signals
AD1859
Figure 13. Interface to L64111
Figure 14 shows the suggested interface to the Philips SAA2500 MPEG audio decoder IC. The SAA2500 supports 18 bits of data using an I2S compatible output format.
SCK WS SD FSCLKIN 256 x FS OR 384 x FS HI LO HI 14 BCLK 13 LRCLK 12 SDATA 9 IDPM0 10 IDPM1 8 18/16
PHILIPS SAA2500
AD1859
The IDPM0, IDPM1, 18/16, and DEEMP control inputs are normally connected HI or LO to establish the operating state of the AD1859. They can be changed dynamically (and asynchronously to the LRCLK and the master clock) as long as they are stable before the first serial data input bit (i.e., the MSB) is presented to the AD1859. REV. A -11-
Figure 14. Interface to SAA2500
AD1859
Figure 15 shows the suggested interface to the Zoran ZR38000 DSP chip, which can act as an MPEG audio or AC-3 audio decoder. The ZR38000 supports 16 bits of data using a leftjustified output format.
SCKB ZORAN ZR38000 WSB SDB SCKIN 256 x FS LO HI LO 14 BCLK 13 LRCLK 12 SDATA 9 IDPM0 10 IDPM1 8 18/16
DA-BCK C-CUBE CL480 DA-LRCK DA-DATA DA-XCK 256 x FS OR 384 x FS LO LO LO
14 BCLK 13 LRCLK 12 SDATA 9 IDPM0 10 IDPM1 8 18/16
AD1859
AD1859
Figure 16. Interface to CL480
Layout and Decoupling Considerations
Figure 15. Interface to ZR38000
Figure 16 shows the suggested interface to the C-Cube Microsystems CL480 MPEG system decoder IC. The CL480 supports 16 bits of data using a right-justified output format.
The recommended decoupling, bypass circuits for the AD1859 are shown in Figure 17. Figure 17 illustrates a connection diagram for systems which do not require de-emphasis support. The recommended circuit connection for system including deemphasis is shown in Figure 18.
+5V ANALOG 1F 0.1F 23 AVDD 12 SDATA 14 BLCK DSP OR AUDIO DECODER 13 LRCLK 9 IDPM0 10 IDPM1 8 18/16 DVDD 17 30 (CHIP RESISTOR PREFERRED) +5V DIGITAL 0.01F 1F 6
CONTROLLER
20-64pF 27MHz
20-64pF
20
19
21
16
15 FILT 28 FGND 27 CMOUT 1 NC 5
10F
0.1F
AGND CDATA CCLK CLATCH XTALI/MCLK XTALO
10F
0.1F 10F
BIAS VOLTAGE FOR EXTERNAL USE
AD1859 AD1859
NC 24 OUTL 4 EMPL 3 OUTR 25 1k 2.2nF
LEFT LINE OUTPUT 10F RIGHT LINE OUTPUT
DGND 18
NC 22
PD/RST 11
MUTE 7
DEEMP 2
EMPR 26
1k
2.2nF
CONTROLLER
Figure 17. Recommended Circuit Connection (Without De-emphasis)
+5V ANALOG 1F 0.1F 23 AVDD 12 SDATA 14 BLCK DSP OR AUDIO DECODER 13 LRCLK 9 IDPM0 10 IDPM1 8 18/16 DVDD 17 30 (CHIP RESISTOR PREFERRED) +5V DIGITAL 0.01F 1F DGND 18 NC 22 PD/RST 11 MUTE 7 DEEMP 2 6 20 19 21 16 20-64pF 27MHz 15 FILT 28 FGND 27 CMOUT 1 NC 5 10F 0.1F 1F 1k 2.2nF 470 33nF NPO 470 33nF NPO 10M 1F 10M RIGHT LINE OUTPUT BIAS VOLTAGE FOR EXTERNAL USE 10F 0.1F 20-64pF
CONTROLLER
AGND CDATA CCLK CLATCH XTALI/MCLK XTALO
AD1859
NC 24 OUTL 4 EMPL 3 OUTR 25 EMPR 26
LEFT LINE OUTPUT
1k 2.2nF
CONTROLLER
OPTIONAL DE-EMPHASIS CIRCUIT SHOWN
Figure 18. Recommended Circuit Connection (With De-emphasis)
-12-
REV. A
AD1859
PCB and Ground Plane Recommendations
tDBH
BCLK
tDBP tDBL tDLH tDDS
MSB MSB-1
The AD1859 ideally should be located above a split ground plane, with the digital pins over the digital ground plane, and the analog pins over the analog ground plane. The split should occur between Pins 6 and 7 and between Pins 22 and 23 as shown in Figure 19. The ground planes should be tied together at one spot underneath the center of the package with an approximately 3 mm trace. This ground plane strategy minimizes RF transmission and reception as well as maximizes the AD1859's analog audio performance.
tDLS
LRCLK SDATA LEFT-JUSTIFIED DSP SERIAL PORT STYLE MODE
tDDH
Figure 21. Serial Data Input Port Timing DSP Serial Port Style
CMOUT DEEMP EMPL OUTL NC AGND MUTE 18/16 IDPM0
1 2 3 4 5 6 7 8 9
28 FILT 27 FGND
ANALOG GROUND PLANE
26 EMPR 25 OUTR 24 NC 23 AVDD 22 NC 21 CLATCH 20 CDATA
The serial control port timing is shown in Figure 22. The minimum control clock HI pulse width is tCCH, and the minimum control clock LO pulse width is tCCL. The minimum control clock period is tCCP. The control data minimum setup time is tCSU, and the minimum control data hold time is tCHD. The minimum control latch delay is tCLD, the minimum control latch LO pulse width is tCLL, and the minimum control latch HI pulse width is tCLH.
tCCL
CCLK
IDPM1 10 PD/RST 11 SDATA 12 LRCLK 13 BCLK 14
DIGITAL GROUND PLANE
19 CCLK 18 DGND 17 DVDD 16 XTALI/MCLK
tCCP
tCCH tCSU
CDATA LSB
15 XTALO
tCHD
tCLH tCLD tCLL
Figure 19. Recommended Ground Plane
TIMING DIAGRAMS
CLATCH
The serial data port timing is shown in Figures 20 and 21. The minimum bit clock HI pulse width is tDBH, and the minimum bit clock LO pulse width is tDBL. The minimum bit clock period is tDBP. The left/right clock minimum setup time is tDLS, and the left/right clock minimum hold time is tDLH. The serial data minimum setup time is tDDS, and the minimum serial data hold time is tDDH.
tDBH
BCLK
Figure 22. Serial Control Port Timing
tDBP tDBL
The master clock (or crystal input) and power down/reset timing is shown in Figure 23. The minimum MCLK period is tMCP, which determines the maximum MCLK frequency at FMC. The minimum MCLK HI and LO pulse widths are tMCH and tMCL, respectively. The minimum reset LO pulse width is tPDRP (four XTALI/MCLK periods) to accomplish a successful AD1859 reset operation.
tDLS
LRCLK SDATA LEFTJUSTIFIED MODE SDATA I 2 SJUSTIFIED MODE SDATA RIGHTJUSTIFIED MODE
tMCH XTALI/MCLK
tMCP
tDDS
MSB MSB-1
tMCL PD/RST
tDDH tDDS
MSB
tPDRP
tDDH
tDDS
MSB
tDDS
Figure 23. MCLK and Power Down/Reset Timing
LSB
tDDH
tDDH
Figure 20. Serial Data Port Timing
REV. A
-13-
AD1859
TYPICAL PERFORMANCE
Figures 24 through 27 illustrate the typical analog performance of the AD1859 as measured by an Audio Precision System One. Signal-to-Noise (dynamic range) and THD+N performance is shown under a range of conditions. Note that there is a small variance between the AD1859 analog performance specifications and some of the performance plots. This is because the Audio Precision System One measures THD and noise over a
0 -10 -20 -30 -40 -50 FS = 44.1kHz FFT @ -0.5dBFS
20 Hz to 24 kHz bandwidth, while the analog performance is specified over a 20 Hz to 20 kHz bandwidth (i.e., the AD1859 performs slightly better than the plots indicate). Figure 28 shows the power supply rejection performance of the AD1859. The channel separation performance of the AD1859 is shown in Figure 29. The AD1859's low level linearity is shown in Figure 30. The digital filter transfer function is shown in Figure 31.
0 -10 -20 -30 -40 FS = 44.1kHz THD+N vs dBFS @ 1kHz
dBFS
-70 -80 -90 -100 -110 -120 -130 -140 0 2k 4k 6k 8k 10k 12k 14k FREQUENCY - Hz 16k 18k 20k
dBFS
-60
-50 -60 -70 -80 -90
-100 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
AMPLITUDE - dBFS
Figure 24. 1 kHz Tone at -0.5 dBFS (16K-Point FFT)
0 -10 -20 -30 -40 -50
dBFS
Figure 27. THD+N vs. Amplitude at 1 kHz
-40
FS = 44.1kHz FFT @ -10dBFS
-45 -50 LEFT CHANNEL -55
-70 -80 -90
dBFS
-60
RIGHT CHANNEL -60 -65 -70 -75 -80
-100 -110 -120 -130 -140 0 2k 4k 6k 8k 10k 12k 14k FREQUENCY - Hz 16k 18k 20k
0
2k
4k
6k
8k 10k 12k 14k FREQUENCY - Hz
16k
18k
20k
Figure 25. 1 kHz Tone at -10 dBFS (16K-Point FFT)
0 -10 -20 -30 -40 dBFS -50 -60 -70 -80 -90 -100 -110 0 2k 4k 6k 10k 12k 14k FREQUENCY - Hz 8k 16k 18k 20k FS = 44.1kHz THD+N vs FREQ @ -0.5dBFS
Figure 28. Power Supply Rejection to 300 mV p-p on AVDD
0 -10 -20 -30 -40
dBFS
FS = 44.1kHz
-50 -60 -70 -80 -90
-100 -110 -120 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k FREQUENCY - Hz
Figure 26. THD+N vs. Frequency at -0.5 dBFS
Figure 29. Channel Separation vs. Frequency at -0.5 dBFS
-14-
REV. A
AD1859
0 -10 -20 -30 -40 -50
dBFS
100 90
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 0.0
-70 -80 -90
10 0%
-100 -110 -120 -130 -140 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k FREQUENCY - Hz
dBFS
-60
0.5
1.0
1.5 FS
2.0
2.5
3.0
3.5
Figure 30. 1 kHz Tone at -90 dBFS (16K-Point FFT) Including Time Domain Plot Bandlimited to 22 kHz
Figure 31. Digital Filter Signal Transfer Function to 3.5 x FS
Application Circuits
Figure 32 illustrates a 600 ohm line driver using the Analog Devices SSM2017 and SSM2142 components. Figure 33 illustrates a "Numerically Controlled Oscillator" (NCO) that can be implemented in programmable logic or a system ASIC to provide the synchronous bit and left/right clocks from 27 MHz for MPEG audio decoders. Note that the bit clock and left/right clock outputs are highly jittered, but this jitter should be
C11 100n C12 100n +15V 17 DVDD 14 13 12 10 9 8 21 20 19 11 2 7 16 15 23 AVDD OUTL 4 3 1Vrms R1, 2k49 3 1 8 2 7
+IN RG1 V+
perfectly acceptable. MPEG audio decoders are insensitive to this clock jitter (using these signals to clock audio data from their output serial port, and perhaps to decrement their audio/video synchronization timer), while the AD1859 will reject the left/right clock jitter by virtue of its on-chip digital phase locked loop. Contact Analog Devices Computer Products Division Customer Support at (617) 461-3881 or cpd_support@analog.com for more information on this NCO circuit.
+15V C5 100n
+5VDD
+5VCC
C6 100n 5Vrms 4 VIN
6 +V +OUT +SENSE 8 7
BCLK LRCLK EMPL SDATA IDPM1 IDPM0 AD1859-JR 18/16 OUTR CLATCH EMPR CDATA CCLK PD/RST DEEMP MUTE XTALI/MCLK XTALO DGND 18
6
OUT REF RG2 V- 5 -IN
4 25 26 1Vrms C8 100n
U2 SSM2017P
U4 SSM2142P
3 GND 5 -SENSE -OUT -V
2 1
-15V +15V 7
+IN RG1 V+
C7 100n -15V
J1 P1 C4 100n 1 2 3 4 5 1 2 3 4 5
P2 J2 1 2 3 4 5 1 2 3 4 5
R3 600
CMOUT FILT FGND AGND 6
1 28 27
VREF
2.25V R2, 2k49
3 1 8 2
6 +15V
OUT REF RG2 V- 5 -IN
4
U3 SSM2017P
5Vrms 4
C3 100n
R4 600
C9 100n
+ - 47 C10 C1 100n -15V VIN
6 +V +OUT +SENSE 8 7
MAX OUTPUT EACH CHANNEL 10Vrms (166.7mV V = +22dBm) INTO 600
U5 SSM2142P
3 GND 5 -15V -SENSE -OUT -V
2 1
C2 100n
Figure 32. 600 Ohm Balanced Line Driver
REV. A
-15-
AD1859
T 13 N [12..0] Q BCLK
+
13-BIT ADDER
27 MHz MSB SELECT K BUS WHEN K < N (MSB = 0) SELECT R BUS WHEN K > N (MSB = 1)
1 R BUS 13 M [12..0] 13 RI BUS 2 TO 1 SELECTOR K BUS 13 13-BIT LATCH
+
13-BIT ADDER
0
13
+
L BUS
27MHz
Figure 33. Numerically Controlled Oscillator Circuit
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Wide-Body SO (R-28)
28-Lead Shrink Small Outline Package (SSOP) (RS-28)
0.7125 (18.10) 0.6969 (17.70)
28 15
0.41 (10.50) 0.39 (9.90)
0.2992 (7.60) 0.2914 (7.40)
0.419 (10.65) 0.394 (10.00)
28
15
0.32 (8.20) 0.29 (7.40)
1
14
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.029 (0.74) x 45 0.010 (0.25)
0.079 (2.0) MAX
PIN 1
0.073 (1.85) 0.065 (1.65)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
0.020 (0.49) 0.013 (0.35)
SEATING 0.0125 (0.32) PLANE 0.0091 (0.23)
8 0
0.050 (1.27) 0.016 (0.40)
0.002 (0.05) MIN 0.026 (0.65) BSC 0.015 (0.38) SEATING 0.009 (0.22) PLANE 0.01 (0.25) 0.004 (0.09)
0.22 (5.60) 0.20 (5.00)
8 0
0.037 (0.95) 0.022 (0.55)
-16-
REV. A
PRINTED IN U.S.A.
C2123-18-4/96
_
13 13

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